资源列表
practica1
- ESTA ES LA DECIMO CUARTA PRACTICA DE LAB 1
led
- 是基于VERILOG的LED灯控制很简单的-LED lights are controlled based VERILOG very simple
BI08D708048AD_V1_IPCore
- 基于SDRAM+CPLD+STM32的VGA显示的-SDRAM+ CPLD+ STM32 VGA-based displays
cordic_IP_EP1C
- verilog编写的调用cordicIP核实现sin信号的完整工程-call cordicIP sin signal to achieve complete nuclear engineering verilog prepared
cycloneiii_3c16_signal
- 基于FPGA，DDS原理的双路正弦波信号发生器，含有与msp430通信模块程序。-Based on FPGA, DDS principle of dual sine wave signal generator, communication modules contain msp430 procedures.
SCHK
- 10位序列检测器，有序列产生，分频器，按键消抖，序列检测，数码管扫描等几个模块构成，设计天津工业大学课程设计-10 sequence detector with sequence generation, dividers, key debounce, sequence detection, digital scanning, and several other modules, curriculum design, Tianjin Polytechnic University
chap1
- 《VHDL编程实例》一书的范例文件,第一章内容-" VHDL programming examples," a book of sample files, the first chapter
chap2
- 《VHDL编程实例》一书的范例文件,第二章内容-" VHDL programming examples," a book of sample files, the second chapter
chap3
- 《VHDL编程实例》一书的范例文件,第三章内容-" VHDL programming examples," a book of sample files, the contents of Chapter III
chap4
- 《VHDL编程实例》一书的范例文件,第四章内容-" VHDL programming examples," a book of sample files, the contents of Chapter IV
chap5
- 《VHDL编程实例》一书的范例文件,第五章内容-" VHDL programming examples," a book of sample files, the contents of Chapter V
JCONTROL_24
- 256分步步进电机开环控制系统 所需的需存入ROM的COS值-256 by step motor open loop control system is required to be deposited in the cosine value of the ROM