资源列表
EWB-sequence-11000011generator
- 使用Electronics Workbench 5.0电子仿真软件(EWB)设计的序列信号发生器。-Using electronic simulation software Electronics Workbench 5.0 (EWB)design a sequence signal generator.
ffirr_166i
- fir低通滤波器 用于dspbuilder pll：25nss data 400khz sin 10.8khz 已通过测试。 -fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.
8bit-cpu-of-mul-and-div
- 包含跳转，乘法，除法8位CPU以及一些基本的逻辑运算功能-includes Jump, multiplication, division eight CPU and some of the basic logic operations
GFEConsMulTaps
- 用于生成GF(2^m)有限域中常数乘法器的Verilog HDL源文件的C程序
CPUInterfaceDesignWithVHDL
- 采用VHDL设计的CPU接口电路，源代码-CPU interface circuit, Designed using VHDL。 the source code
src
- verilog 通过串口控制VGA显示黑白机彩色棋盘 开发板是Xilinz RQ208-Color display in black and white machine control board through the serial port VGA Development Boards
32_bit_complex_multiplier
- 一款32位复数乘法器，用verilog写的。-32_bit complex multiplier,written in verilog HDL.
minicore
- minicore为一个加法器的最小结构，含有移位RAM 和调试的TB 程序等。-minicore for a minimum adder structure, containing translocation TB of RAM and debug procedures.
fdivision
- 使用Verilog语言实现20分频的代码，简单易懂，经过medolsim仿真，可正确输出预期的波形，实现20分频。-Using the Verilog language to achieve 20 points frequency code, easy to understand, after medolsim simulation, correctly anticipated the output waveform frequency to achieve 20 points.
Protection-Logic
- 电力电子设备保护逻辑，实现快速封锁PWM脉冲-Protection logic for Power Electronic Device.
Alu-with-seven-segmetn-output
- This contains VHDL source code for a simple arithmetic logic unit. the input and results are displayed on a 4 digit 7 segment display. The user controls the input throug the use of switches. This design was created for the nexys 2 fpga but can be eas
71V25761_Verilog_99056.tar
- SSRAM Simulation Model