- Code vb使用vsmenu控件的源码
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- adodcocx This an Activex Control (.ocx) and a demo application that uses it. The control provides the ability to navigate
- eZ430-RF2500(IAR-Source)-v1.02 msp430 ez430
- matlabtomode In this context
- Chrysanthe34mum safpikejsoefjwlekfjwi23134ij3
资源列表
color converter
- The main purpose of the core is a color transform tasks such as CIE XYZRGB, different RGBRGB and RGBYCbCr operations. The main part of color conversions from one to another color system concludes in 3x3 matrix multiplication with vector addition. The
vhdl
- 32位33Mhz PCI接口程序设计参考,芯片是Lattice -32-bit 33Mhz PCI interface programming reference chip is Lattice
rtl
- STOPWATCH,alarm,clock 功能的数字钟-General Digital Clock Clock setting with Switch – Use Key_up and Key_down key to change the number – Use Key_right and Key_left key to change the position – Use set key to start Clock Alarm Function – Use Ala
Example-b8-4
- ModelSim的波形比较的功能可以将当前仿真与一个参考数据(WLF文件)进行比较,比较的结果可以在波形窗口或者列表窗口中查看-Comparison of the ModelSim wave functions , compare the results can be viewed on the waveform window or the list window
nios_web
- 基于Nios的CPU软核设计实现,quartus-Nios soft core CPU based on the design and implementation, quartusII
ofdm4
- 16QAM加上IFFT调制的OFDM的VHDL的代码,编译通过,可以拿去仿真借鉴-Plus IFFT OFDM 16QAM modulation of the VHDL code, compile, you can take the simulation draw
NiosII
- 非常不错的nois设计程序代码 通过 可以尝试下载-maybe, helpful for you
mipsinverilogandvhdl
- mips prcessor in Verilog and vhdl-mips prcessor in vhdl and Verilog
ZBTSRAM
- 高速同步SRAM控制器参考设计VHDL代码-High-speed synchronous SRAM controller reference design VHDL code
spi_verilog
- spi通信协议的设计参考,对于初学者可以以此为参考进行设计,代码可在仿真软件中验证(modelsim、VCS等)。-Spi communication protocol design reference for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
exp11
- lcd实验的.h文件,经验证,已经完全正确的了。-lcd experiment. h file, experience certificate, has been completely correct.
8bit_decoder
- Verilog code for 3*8 Decoder Circuit with testbench file-Verilog code for 3*8 Decoder Circuit with testbench file....
