资源列表
16bit-CLA
- 16 bit carry look ahead adder verilog code
8051pwm
- 8051pwm.rar，带有用51系列单片机来产生pwm波形的c程序，-8051pwm.rar, with the use of 51 computers to generate the pwm waveform c procedures
FPGAcode
- 函数，任务，有限状态机，状态机接口设计，SRAM设计FIFO的代码实现-Functions, tasks, finite state machine, the state machine interface design, SRAM FIFO design code implements
sdram
- SDram的读写控制。站长我是一名初学者，而且对其很感兴趣，但作为一个初学者起始是万般艰难的，我就只有这一源代码，奉上。望转正！万分谢谢。-The control SDram, reading and writing
Whats-New-in-CORE-Generator-and-IP
- ise13.1中有什么新的ip核和资源，希望用ise的朋友能好好看看。-ise13.1 What' s new in the ip nuclear and resources in the hope that friends can have a good look at ise.
UART_Xilinx_vhd
- USB IPcoreIP核 包含文档(带说明)-USB IPcoreIP core includes a document (with instructions)
Xilinx_DCM
- 基于ise 10.0来实现Xilinx的时钟设计和管理-Xilinx dcm digital clock manager
Generator
- This a simple pulse generator. It generates a pulse-This is a simple pulse generator. It generates a pulse
Verilog_uart
- 异步通讯串口调试程序，用VERILOG写的，保证能用-Asynchronous communications serial port debugger, using VERILOG written assurance can be used
SingleCycle8bitProcessor
- Simple 8-bit Single Cycle Processor in Verilog HDL
PARITY-CHECK
- this vhdl code for parity check is very helpful while coding and decoding , Implementing this in an cpld of fpga is very easy and it can be used as a subpart of any embededd design such as multiplexers , Decoders etcv -this vhdl code for parity check
EDA
- EDA重点内容，附带HDML文件-EDA highlights, with HDML files! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !