资源列表
LAB3
- THAT IS SOLUTION FOR THE LAB OF DSD LAB 3
sd_models_verilog
- 测试过可用的SD仿真模型，VERILOG语言-SD card simulation modle, test OK
lab3no1
- Design the behavioral type of VHDL code for a 4-bit binary up counter. Include an overflow output signal with your code.
lab1code
- 时钟，可正计数，反记数，每分钟提示一次.时钟通过计数器实现，优化实现进位-a clock which can count on and count off. remain very minute
pcm
- 该程序设计了一个产生PCM码流时序信号的模块，他包括输入端CLK，SET及输出端Q1,Q2,Q3-the program have designed a PCM signal timing modules, including the CLK input, and output SET Q1, Q2 and Q3
machine_project
- verilog代码写的自动售货机。已经调试过了。顶层单元是top。注意其中的商品只有两种。-verilog code written in vending machines. Debugged the. Top-level unit is the top. Note that one of the only two commodities.
sdramcontrol.rar
- 达到时钟频率并发读写速度的SDRAM控制器核,Concurrent read and write speeds up the clock frequency of the SDRAM controller core
yd0601
- 单片机定时计数器的应用，简单的定时计数实验，适合初学者-Microcontroller timer counter application, a simple count of the timing experiments, suitable for beginners
DE2_SD_Card_Audio
- Verilog代码，适合于初学者进行学习，是基于DE2平台的代码。
VHDL
- 基于FPGA的六层电梯控制器系统,-FPGA-based six-story elevator controller system,
chap10
- 《Verilog HDL 程序设计教程》7-"Verilog HDL Design Guide," 7
1bitadder
- 1 bit adder code VHDL