资源列表
test_rtls
- RTl hardware generation
16FFT
- Xilinx的16点傅里叶分析，内有详细说明-The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary compone
00011ipcore51
- 51内核单片机的VHDL语言的实现,从功能到编译都有详细说明,包括源码
SEG7
- 自己设计的数字钟，用6个数码管显示，并且可以调整时间-Digital clock of their own design, with six digital display, and can adjust the time
zuyuan
- 这是一个实现有限状态机的verilog编程的程序-This is a realization of finite state machine programming procedures verilog
ethernet10-100M-IP-core
- 以太网10-100M IP核Verilog源码，可综合-Ethernet 10-100M IP core Verilog source code can be integrated
Actel_DirectCore_CORESPI_4.2.116
- Actel DirectCore CORESPI 4.2.116 Verilog and VHDL RTL source files for SPI controller on APB
ethernet_tri_mode.tar
- 用FPGA verilog hdl实现千兆以太网MAC。
MAX_II_using_the_example_of_the_UFM_block
- BJ-EPM240V2实验例程以及说明文档实验之十四MAX II的UFM模块使用实例-BJ-EPM240V2 experimental test routines as well as documentation of the MAX II 14 UFM module uses examples
two_dimension_fpga
- FPGA实现模糊控制,可以应用于各种控制相关工程之中-FPGA Implementation of Fuzzy Control
以太网10-100M IP核Verilog源码
- 以太网10-100M IP核Verilog源码，可综合
random
- 用简单的线性反馈移位寄存器实现了伪随机数的生成…(The pseudo random number is generated by a simple linear feedback shift register)