资源列表
16_bits_CPU_verilog_code
- 利用Verilog设计的16位CPU的设计案例-the example of 16 bits CPU using verilog
ss
- 这里的代码对大家有帮助啊 快来看看吧 谢谢啦 哈哈 关于波形的的代码-thanks you
div7
- VERILOG代码 七分频电路设计通用分频器值得一看-DIV7 circle
GenDEC.RTL
- Tristate Bus -Tristate Bus Tristate Bus
parall_ad_da
- 在和众达SEED—XDTK平台上，基于XC4VSX25的 平行模数，数模转换程序-In and Jones SEED-XDTK platform, based on the parallel XC4VSX25 modulus, digital-analog conversion process
key
- 在和众达SEED-XDTK平台上，基于XC4Vsx25的按键扫描驱动程序。-In and Jones SEED-XDTK platform, based on the key scan XC4Vsx25 driver.
lcd
- 在和众达SEED-XDTK平台上，基于XC4Vsx25的液晶驱动程序。-In and Jones SEED-XDTK platform, based on XC4Vsx25 liquid crystal driver.
call
- verilog实现电梯的召唤功能，在quantusII环境下运行，包含工程文件和其他子文件-verilog to achieve the elevator call functions in quantusII environment to run, including engineering documents, and other sub-documents
dot
- 在和众达SEED-XDTK平台上，基于XC4Vsx25的点阵驱动程序。-In and Jones SEED-XDTK platform, based on the lattice XC4Vsx25 driver.
led
- 在和众达平台上，基于XV4FPGA开发外围驱动，使得led管循环点亮。-And Jones in the platform, based on the development XV4FPGA external drive, making led tube light cycle.
xapp525
- xapp525 from xilinx website: SPI-4.2 to Quad SPI-3 Bridge
xapp737
- xapp737 from xilinx website : SPI-4.2 to Quad SPI-3 Bridge in Virtex-4 FPGAs