资源列表
alu1
- 本文是基于vhdl的8位cpu ip core设计alu-This article is based on the 8 vhdl cpu ip core design alu
lock
- 本人编写的verilog程序密码锁，已仿真通过，欢迎大家下载并指正批评，互相学习。-I write verilog program locks have been through simulation, welcome to download and correct criticism, learn from each other.
binary_to_BCD
- 本人编写的2进制转换为BCD码的verilog程序，绝对可用，已测试通过。-I write binary to BCD verilog program, absolutely free, have been tested.
elevator
- 本人编写的verilog电梯程序，已仿真通过，欢迎大家下载学习，批评指正。-I write verilog lift procedures have been through simulation, welcome to download the study, criticism.
ad_ctr
- 本人编写的ad9280控制器程序，经过硬件测试通过，欢迎大家下载学习。-I prepared ad9280 controller program, after the hardware test, welcome to download the study.
sdk_echo_lwip
- echo_server,基于xlinx的sdk编程，采用lwip完成了tcpip协议，包含完整的源代码。-echo_server, based xlinx the sdk programming, using lwip completed tcpip agreement contains the complete source code.
sdk_memory_test
- 内存测试程序，包含完整的源码。在xilinx的sdk环境下运行-Memory testing procedures, including complete source code. Run under the xilinx sdk environment
socket_apps
- socket编程例程，在xilinx的sdk环境下实现，简单易懂，可作为设计参考-socket programming routines to achieve in the xilinx sdk environment, easy to understand, can be used as a reference design
verilog
- verilog课件，讲述语言的详细资料和应用，对FPgA的设计有很好的作用-verilog courseware, details about the languages and applications designed for FPgA have a good effect
aadd4
- verilog 描述的超前进位加法器，速度较快，可综合-lookahead adder verilog descr iption, faster, can be integrated
adsub4
- verilog编写的可综合的加减法器 速度较快-verilog written on subtraction can be integrated faster
alu
- verilog 编写的 可综合的ALU单元 可执行加减与或非 5种运算-verilog prepared by the ALU unit can be integrated with non-executable plus or minus five kinds of computing