资源列表
src
- 32位加法器,verilog HDL，初级用，-32-bit adder, verilog HDL
QuartusII12.0-
- 此文件为QuartusII12.0 安装及使用教程，包括了安装指南及建立文件过程。-This file is installed and used QuartusII12.0 tutorials, including installation guides and create a document processes.
12864
- 能够实现，12864显示简单得中文字符。适合于初学者学习，研究。-Can be achieved, 12864 shows simple Chinese characters. Suitable for beginners to learn and study.
Light-water
- 流水灯，非常好用，在quarts上完美运行，verilog语言编程好好地-Light water
s_machine
- 单进程Moore状态机，st0到st4的五个不同状态间的转换。性能良好的同步时序逻辑模块； 与VHDL的其他描述方式相比，状态机的VHDL表述丰富多样、程序层次分明，结构清晰，易读易懂-Single process Moore state machine, st0 to st4 five conversion between different states. Good performance of synchronous sequential logic module Compare
coder83
- 基于VHDL的8-3优先编码器模块，din0-din7八位二进制输入编码后输出三位编码结果。采用正逻辑设计，高电平有效。-8-3 priority encoder module, based on VHDL din0- din7 eight binary input encoded output three coding results. Adopt positive logic design, high level effectively.
Verilog-language--de-CPU
- 基于verilog语言的FPGA开发，平台在QuartusII上，对SDRAM的读写-Verilog language based FPGA development platform on QuartusII, the SDRAM read and write
source
- Single Channel LVDS Tx - Source Code-Single Channel LVDS Tx- Source Code
piano
- piano musical con la 5 octava
hoy
- es la practica de laboratorio 1
frecuenciometro
- es la practica de laboratorio 1
pprobar
- ES A PRACRICA 2 DEL LABORATORIO DE DIGITAL