资源列表
keyscan
- verilog 写的keyscan代码，转载的，可供大家学习一下！-verilog code written keyscan, reproduced, and for them to learn about! Thanks
SDRAMverilog
- SDRAM 驱动，Verilog HDL源码-SDRAM-driven, Verilog HDL source code
fw
- one hot state machine.. is the project name. this is a file to execute in vhdl... it is very useful in many applications, just hav a look guys.
EDA
- 以上资料是是有关于FPGA芯片与硬件的链接原理图，对开发FPGA有很重要的作用。还有一些相关软件程序供参考-The above information is on the FPGA chip and the hardware link diagram, on the development of FPGA a very important role. There are a number of related software programs for reference
edaok_UART_FPGA
- 用FPGA实现UART的串口通信，可以设置数据位，校验位，奇偶校验等-With the FPGA to achieve UART serial communication, you can set the data bits, parity bit, parity, etc.
symbolic_decomposition
- 本文件包括基于verilog的符号分解源码，即实验报告和实验结果-symbolic_decomposition
DE2_i2sound
- 基于FPGA的音频信号A/D转换，适用于DE2开发板。-FPGA-based audio signal A/D conversion, for DE2 development board.
dds
- 用vhdk编写的dds信号发生器的代码，用fpga实现dds功能-Dds with vhdk signal generator written in code, using fpga implementation dds feature
xuliejianceqi
- vhdl编写的序列检测器，包括模块以及顶层文件-vhdl prepared by the sequence detectors, including the module, as well as the top-level document
shouhuoji
- 使用文本方法编写的自动售货机的vhdl代码-Use a text methodology for the preparation of the vhdl code for a vending machine
signalgenerator
- 使用VHDL编写的函数信号发生器，该模块使用文本输入-Written using the VHDL function signal generator, the module uses text input
tiaozhijietiaoqi
- 本例子设计了调制解调器的VHDL代码，改模块完全使用文本输入-This example is designed modem VHDL code, and changed completely the use of text input module