资源列表
sopc_builder_tutorial
- This application ready to run about use altera monitor program with de2 sample processor
tut_sopc_introduction_vhdl_2
- This book descripe how use altera monitor program with sopc fpga by verilog language
sopc_altera_monitor_program
- This book descripe sample example to use altera monitor wih quartes
10_code_ALTERA7128SLC84
- 10个FPGA实验的源代码，用VHDL编写，是一个试验箱的开发手册-10 CPLD experiment, the source code
s3edisp_schem
- This document is a entire schematic of SPARTAN3 DSP Development Board.
vend
- 自动售货机，根据所要的东西，自动收费，并进行找零-Vending machine, according to what you want to automatically charge and conduct Keep the change
CPU_16_Beta_1.0
- VHDL CPU 16 16位的简易CPU 开发工具为Xilinx-VHDL CPU 16 a simple CPU in VHDL
Anne
- write "AnnE" with 7 segment display using vhdl code at spartan 3e
FPALU_TestBench
- floating point unit
rom
- 一个ROM读数据代码，简单，一目了然，一起学习-A ROM read data code, simple, clear, along with learning
mb
- 简单秒表(1分钟)，希望对初学者有帮助，VHDL-Simple stopwatch (1 minute), want to be helpful for beginners, VHDL
jiaot
- 一个很简单的交通灯控制器，容易理解，在EP1C3T140C8上跑过-A very simple traffic light controller, easy to understand, in the EP1C3T140C8 ran