资源列表
SDRAM
- 用Verilog HDL语言编写的SDRAM控制器，在DE2-70的开发板上实现。-SDRAM Controller with Verilog HDL language, DE2-70 development board.
PLL
- quartus II中IP核的使用案例，在程序里边调用了PLL核进行时钟的管理。-Quartus II IP core use cases, called in the program inside the PLL core clock management.
DIVISION
- 用verilog HDL语言编写的实现两个数相除的例程，在DE-70开发板上实现。-Verilog HDL language routines divide two numbers in the DE-70 development board to achieve.
kechengsheji
- 电子密码锁是基于FPGA实验平台设计的，能够实现密码输入、密码校验、密码设置和更改密码，错误报警和密码错误三次自锁键盘并报警的功能。-Electronic locks, FPGA-based experimental platform can be achieved password entry, password verification, password settings, and change your password, false alarms and the wrong passw
uartfifo
- FPGA采用FIFO实现UART，对于大量异步数据的采集传输很有帮助-A usart design of FPGA using fifo,it can be used in massed asychronous data collect.
VGA_GAME
- 基于FPGA，VGA,PS2的贪吃蛇游戏verilog源码，内附说明-Based on FPGA, VGA, PS2 Snake game Verilog source code, containing a descr iption
8051core-Verilog
- Verilog实现8051 core.基本可用，基于Altera硬件平台实际验证通过。-how to implement 8051 core via verilog.
shiyansan
- 简易数字频率计 实验设计 数字系统设计 采用模块化设计 -Simple digital frequency meter experimental design digital system design is modular in design
traffic
- 交叉口多相位信号控制机，包含分频模块及主控模块，各方向绿灯时间不同，12个led灯分别控制-Multi Phase signal controller with frequency module and main control module, the green light in each direction at different times, 12 led lights control
CAN-Bus-IP-Core
- ＦＰＧＡ中ＣＡＮ总线的ＩＰ核，加入工程中既可以使用。-CAN bus in FPGA IP, can be used to join the project
pianoend
- 用8×8点阵显示“1 2 3 4 5 6 7”七个音符构成的电子琴键盘。其中点阵的第一列用一个LED点亮表示音符“1”，第二列用二个LED点亮表示音符“2”，依此类推-88 dot matrix display " 1 2 3 4 5 6 7" of seven notes of the piano' s keyboard. The first column of the lattice with a LED lit notes, " 1" , notes
1_lab1
- （1）熟悉S6 CARD实验板； （2）熟悉ISE集成开发环境； （3）3比特加法器仿真与上板实验； （4）m序列产生器仿真与在板Chipscope调试 -(1) be familiar with the S6 CARD experimental board (2) be familiar with ISE Integrated Development Environment (3) 3-bit adder simulation experiment on board (4