资源列表
基于vhdl的抽奖程序
- 用vhdl语言编写的抽奖程序，以led灯的亮灭状态显示抽中哪个灯
zedboard
- xilinx的zed板详细开发资料，对初学者和开发人员都有帮助-The Xilinx zed board detailed development information, helpful for beginners and developers
BotelloProyecto
- Unipolar Stepper Motor Driver in VHDL, with CCW,Step-number,Half/Complete Steps and Velocity selector
test_wuline
- 用 verilog语言实现直线的显示与反走样，用的是wu算法，适用于fpga实现-The Verilog language line display with anti-aliasing, wu algorithm, suitable for fpga implementation
counter-0-9999-on-DE1
- Hello its simple counter for DE1 boards
CHANNEL_ESTIMATION_PROJECT
- 基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来-Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it
CPU8bit
- 复旦大学 计算机体系结构实验 8位cpu-8bit cpu
SDK_lwip_echo_server
- Xilinx spartan-3e开发板，EDK的配置，及SDK的一个TCP echo server的实例。运用LWIP（Light Weight IP）轻型IP协议。-Xilinx Spartan-3e development board the EDK' s configuration, and the SDK a TCP echo server instance. The use of the the light IP protocol of LWIP (Light Weight I
te_copy
- 利用verilog编写的频率计，测量信号通过管脚输入，8个七段管显示频率，可以实现1-50M频率的精确测量-A frequency indicator based on verilog HDL, measured signal connect the chip by the input pin and display the result on the seven segment.It could realize the frequency measurement accurately.
FPGA-FIFO-VHDL
- 这是一个基于FPGA的异步FIFO设计，利用的VHDL硬件描述语言，内容分析清楚，附带完整代码-This is an FPGA-based asynchronous FIFO design, the use of VHDL hardware descr iption language, content analysis, with complete code
fifo
- 本文档是一个异步FIFO设计的完整工程，利用modelsim仿真软件，分不同的模块-This document is the complete works of an asynchronous FIFO design, the use of the modelsim simulation software, divided into different modules
VHDL-TESTBENCH
- 这是一篇用VHDL编写testbeach测试文件的详细讲解资料，举例讲解详细易懂，很实用-This is a VHDL explain in detail the information writing testbeach test file, for example, to explain in detail to understand, it is practical