资源列表
digital-colok
- 用quartusII编写的vhdl代码，在板子上输出的显示就是数字钟，也可以重置、设置时间。-With written in VHDL quartusII code, the output is the digital clock is displayed on the board, you can also reset, and the time.
add-8
- 在逻辑开发中的八位加法器源代码，即用quartus软件来进行编码实现八位加法器的功能。-Eight adder logic development source code, Coding eight adder Quartus software.
Pld-based-VGA-display
- 基于pld和Verilog语言的VGA显示，内容为雨后彩虹。-Pld-based VGA display
Experiment
- 可编程逻辑器件VHDL实现的3线-8线译码器-VHDL 3-8 priority encoder decoder
4-bit-Multiplier
- IT is a 4 bit multiplier vhdl coding file which is run in altera quatrs - II. in which 4 binary bit is multiplied and waveform can be obtained
WORK4
- 可编程逻辑器件实现VHDL8-3优先编码器-8-3 priority encoder decoder
4-bit-ALU
- it is a 4 bit airthmatic logic unit in which all basic mathematical operation of binary number can done. it is a vhdl code file
4-bit-Ripple-Carry-adder
- it is 4 bit ripple carry adder. it is one type of counter you can say. in which carry is added. it is vhdl code and its waveform which is run in altera quars II.
Melay_1001
- it is Mealy model s vhdl code. and it was implemented and run in Altera quarts - -it is Mealy model s vhdl code. and it was implemented and run in Altera quarts - II
Moore_1001
- it is a moorey model s vhdl code which was implemented and run in altera Quarts - II
Frequency_Div
- it is vhdl code for "frequency divider" which was implemented and run in altera quarts- -it is vhdl code for "frequency divider" which was implemented and run in altera quarts- II
Qep
- 编码盘输入之前的滤波电路与编码盘的技术电路，也可以作为其他功能模块的实现软件滤波-Filter circuit