资源列表
Async_fifo_verilog
- FIFO的用途，分类，一些重要参数，设计的难点和算法-FIFO uses, some important parameters, the difficulty of the design and algorithm
camera_fifo_ctrl
- camera异步接口中FIFO控制部分的源代码-FIFO control section of the source code in the asynchronous interface, camera
fifo_code
- FIFO读空标志和写满标志的计算，memory分配-FIFO read empty flag and filled with flag calculation, memory allocation
SAR-ADC
- Complete Successive approximation Analog to digital converter along with the source code
lw
- 实现抢答器的功能，四人抢答，还有附加功能包括抢答计时，提前抢答预警，到时间停止，记录分数等-you can see
seven_seg
- a seven seg display module
asdasd
- a pibg file that is a seven segment
fib
- 一个基于VHDL编程的可用于FPGA实现的斐波那契数列计算器- implemented a circuit in VHDL that calculates Fibonacci numbers
vhdl-serial
- VHDL串口通信,实现数据的发送与接收，适合FPGA和CPLD芯片的开发-VHDL serial communication
xuliejianceqi
- 在FPGA开发板上用硬件描述语言实现一个状态序列检测器，比如边沿检测器等-FPGA verilog
main
- EP2C35A实验箱基于NIOSII的串行AD_DA编程-EP2C35A experimental box based NIOSII the serial AD_DA programming
test
- dac900驱动，使其产生正弦波，其中关于ram的查询以及pll倍频模块，该代码只是总的调用-DAC900 driver to produce a sine wave, which RAM query and PLL multiplier module, the code is just the total number of calls