资源列表
09_vga
- 基于FPGA（EP4CE15F17C8）的VGA驱动实验，编程语言为Verilog HDL，适合Verilog编程入门学习。-VGA driver based the FPGA (EP4CE15F17C8) experiment, the programming language for the Verilog HDL for Verilog Programming learning portal.
vga
- 一个VHDL的VGA显示程序，设置的分辨率为640*480，这个程序很简单，仅供参考。-A VHDL VGA display, set the resolution to 640* 480, the program is very simple, for reference only.
TEST-CPU-2
- 基于VHDL语言的微指令控制的CPU，16位地址线-VHDL language based on the microinstruction control of the CPU, 16-bit address lines
DE1_synthesizer
- DE1 music synthesizer
Verilog-HDL-huawei-rumen
- 华为入门的verilog资料，希望能给大家带来点小小的收获-Verilog Huawei entry information, I hope we can bring a small harvest
Washer
- 基于VHDL代码的洗衣机，基于Altera的Quartus变异完成，可以烧制入FPGA-VHDL code based on the washing machine, based on Altera' s Quartus variation completed, can be fired into the FPGA
bingzhuanchuan
- 串行转并行算法，自己编写，已经运行成功，算法简单易懂。-Serial to parallel algorithm
ATTEN_CPLD_INIT
- 串行转并行，复位，并行转串行，通道选择，衰减信号，所有代码在一起-Serial to parallel, reset, parallel-to-serial channel selection, signal attenuation, all the code together
shuaijian_FINAL
- 一种基于计算机硬件的verilog程序，主要针对衰减信号，AD5543系列的芯片-A computer-based hardware Verilog procedures, mainly for signal attenuation, AD5543 chip
fuwei
- 复位算法，在不同芯片中，拷入芯片内的程序需要复位，因此本算法适合复位-Reset algorithm, chip program copyed into the chip needs to be reset, the algorithm is suitable for reset
bingzhuanchuan
- 并行转串行的另外一种算法，压缩包内拥有算法的说明，很有效的一种算法-An algorithm of parallel-to-serial another algorithm, compression algorithm package has, very effective
4.18
- verilog的测试工程，实现多种初学者必要的学习编写测试。非常好的菜鸟装备！-the verilog test engineering, beginners necessary to learn to write tests. Very rookie and equipment!