资源列表
yuyin_jiami
- 基于quarusII仿真软件，进行模块化设计，设计达到的目的是对进来的语音信号进行加密处理-Based on quarusII simulation software, modular design, designed to meet the incoming voice signal is encrypted
sin_10k
- 基于FPGA的利用rom进行查询的方式生成一个频率为10KHZ的sin信号，编译成功，并实现功能仿真。-Query based on the the FPGA use of rom generate a frequency of 10 kHz sin signal, compiled successfully and to achieve functional simulation.
fir
- 基于FPGA的低通滤波器的设计，仿真环境是QuartusII9.0。对信号进行低通滤波，编程成功。希望对大家有所帮助-FPGA-based low-pass filter design, the simulation environment QuartusII9.0. The signal is low-pass filtering, the programming was successful. We hope to help
decoder3_8
- 燕山大学VHDL课程设计，3-8译码器简单代码。-Yanshan University VHDL curriculum design, 3-8 decoder simple code.
jiaotongden
- 燕山大学通信工程VHDL课程设计，简易交通灯编程代码。-Communication Engineering, Yanshan University VHDL curriculum design, simple traffic light programming code.
step-machine
- fpga课程设计中的步进电机简易编程代码，VHDL语言。-FPGA curriculum design stepper motor simple programming code, VHDL language.
spi-verilog
- 用Verilog来实现SPI接口电路逻辑，实现主机与从处理器的通信-SPI interface circuit is implemented in Verilog logic between master and slave processor communication
jiaotongdeng
- 交通信号灯自动控制器,能下载到FPGA开发板，自动交通灯控制程序，由VHDL编写，环境为QUTUS2-Traffic signal controller, can be downloaded to the FPGA development board, automatic traffic light control procedures, written by VHDL environment QUTUS2
EDA-Clock
- 基本功能： 1、输入1KHZ的时钟； 2、能显示时、分、秒，24小时制； 3、时和分有校正功能； 4、当计时器运行到59分49秒开始报时，每鸣叫1s就停叫1s，共鸣叫6响；前5响为低音，频率为500HZ；最后一响为高音，频率为1KHZ； 5、可设定夜间某个时段不报时； 6、设定闹钟。 -Basic functions: input 1kHz clock 2, display hours, minutes, seconds, 24-hour clock 3, hou
uart_Verilog
- 基于Verilog的RS232串口通信实验，可发送256位数据，并在Altera的EP4CE15F17C8芯片上验证成功。-Verilog-based RS232 serial communication experiment, 256-bit data can be sent on Altera' s EP4CE15F17C8 chip authentication is successful.
uart_state
- 基于状态机编写的串口通信实验，编程语言是Verilog HDL，可发送八位数据，在Altera的EP4CE15F17C8芯片上验证成功。（与另一个发送256位不同的是这个代码比较突出状态机的使用）。-Prepared by the serial communication experiment based on state machine, the programming language is Verilog HDL can transmit eight bits of data, verif
lcd_spi
- FPGA（EP4CE15F17C8）驱动LCD12864液晶显示实验，利用SPI串行传输数据，显示指定图像。-LCD12864 LCD FPGA (EP4CE15F17C8) driver experimental use the SPI serial transmission of data, display the specified image.