资源列表
cpld-tft
- cpld 驱动 tft lcd 显示，达到显示效果-the cpld drive tft lcd display
fir_16
- fir滤波器-verilog，基于verilog的fir滤波器源码-fir filter-verilog, the fir filter based on the Verilog source code
seg70_ise7_bak
- 7SEGMENT VHDL CODE-THIS CODE VERY GOD FOR DRIVE 7SEG-IN ISE FUNDATION 11.1
VHDL_processor
- 利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.-use VHDL descr iption of a simple microprocessor, can modify the source codes to adjust instruction set, Quartus II can be directly compiled and running.
TimeQuest
- Timequest的应用试验，包含Timequest的例子。-Timequest application testing, including Timequest example.
software
- ddr3 Test program for Altera FPGA Starter Kit
muhammadali_357
- T-flip flop lab done in our campus
test1602
- 1602的VHDL程序！在自己的板子上一测试测试成功！-1602 VHDL program! In their board a test success!
core_arm
- arm核的源代码，非常不错，欢迎下载 arm核的源代码，非常不错，欢迎下载-arm core source code, very good
signal_generator
- signal Generator: it can generate square, sine, saw-tooth, triangular wave forms on spartan 3an board
PIN
- 用VERILIG编写的FPGA串口与电脑通信-Written by VERILIG FPGA serial communication with the computer
dianti
- 实现电梯的相关控制系统，在开发板EGO1上实现，数码管显示相关的楼层和状态-dianti in verilog