资源列表
demod_4psk
- 利用VHDL实现4PSK数字调制技术解调源代码-Using VHDL realize 4PSK demodulation source code
sorter
- Sequential n-deep w-wide unsigned sorter.
sorter_tb
- Test bench for Sequential n-deep w-wide unsigned sorter
Median-Module
- Median Module VHDL code
Clock-experiment
- 数字时钟程序，亲自在实验室做过这个实验，实验成功。-Digital clock program, personally done this experiment in the laboratory, the experiment was a success.
ROBOT_CONTROL
- code for xilinx spartan fpga to make robot path control by detecting obstruction using ultrasonic sensor
fwcode
- high-level data link control procedure VERILOG CODE
HDB3
- HDB3协议的编解码，并有对于频率为32768HZ的仿真图，并且将时钟线数据线合一，并有同步时钟提取的模块。-failed to translate
i2cslave
- i2c slave controller
PWM_IP_TEST
- 自定义PWM的IP核 符合avalon总线格式-Custom PWM IP core is in line with the avalon bus format
RS_FPGA
- RS编码器译码器的FPGA实现原理，优化，在光通讯中应用-failed to translate
uartfifo
- 基于FIFO的串口发送机设计。主要实现一个串口发送器功能，该发送器的数据是从FIFO 中读取的。也就是说，只要FIFO 中有数据，串口发送器就会启动，将数据发送出-FIFO-based serial transmitter design. A serial transmitter function of the transmitter data is read from the FIFO. In other words, as long as there is data in the FIFO,