资源列表
Commandinterface
- SDRAM控制器Verilog员代码，命令生成模块，完成SDRAM控制接口命令的生成-SDRAM controller member Verilog code, order generation module, SDRAM interface complete control orders Generation
shuzizhong
- 在单片机上实现数字钟，时分秒的显示以及整点报时功能。-Realize single-chip digital clock, hour, minute and second of the display, as well as the whole point timekeeping function.
cap_data_model
- Linguagem em VHDL - Capt_data
bpsk_spread_spectrum_modulator_demodulator
- code for bpsk spread spectrum modulator used in cdma -code for bpsk spread spectrum modulator used in cdma ..
426_Onida
- firmware for Onida TV
COMPLETE-UART_16
- the project is complete a UART implementation where 16 UART are connect with top module for aerial applications-the project is complete a UART implementation where 16 UART are connect with top module for aerial applications
s3_bom
- sparten开发板的bom清单，相当详细，各元件的详细描述-sparten bom development board list, very detailed descr iption of each component
PROJECT
- 这是LVDS的测试源文件，经运行后正确。-this is a lvds Programme.
VHDL
- 7段数码显示译码器设计，包裹程序设计，实验目的，内容，图像。-7 digital display decoder design, package design, experimental purposes, content, images.
full-asd
- ABOUT FULL ADDER VHDL CODE
uart
- 9针的rs232与fpga之间的串口通信源程序-Rs232 9 pin serial communication with the source between fpga
verilog_synthesisable_sentence
- verilog可综合及不可综合语句总结，自己总结的verilog编程的一些知识，对初学者比较有用。-learn verilog programming document, a summary of some knowledge of their own, more useful for beginners.