资源列表
vscnfet_1_0_1
- CNFET VS-MODEL verilog-A 描述，用于Hspice仿真模型，优化MOSFET性能- stanford
arm9_compatiable_code
- arm9 compatiable verilog code
dct
- 用vhdl语言来实现了dct离散余弦变换-With VHDL language to achieve the optimal discrete cosine transform
duogongneng
- 多功能波形放生器，产生三种波。方波。。j锯齿波。。正弦波 -Release device function waveform, resulting in three waves. Square wave. . j ramp. . Sine wave
Example-8-2
- Verilog延时建模设计 Example-8-2目录下为设计工程子目录，目录中包含以下内容。 1. Blocking_LHS_Delay：阻塞赋值左式延时。 2. Blocking_RHS_Delay：阻塞赋值右式延时。 3. NonBlocking_LHS_Delay：非阻塞赋值左式延时。 4. NonBlocking_RHS_Delay：非阻塞赋值右式延时。 -Delay Modeling Verilog Design Example-8-2 design engi
5-15
- 用verilog语言实现基于DDS技术的余弦信号发生器，其输出位宽为16比特-Verilog language cosine signal generator based on DDS technology, the output bit width is 16 bits
vga_verilog
- 本示例演示了VGA的控制方法，程序配置后可以在CRT上显示中文汉字等信息。-this example demonstrated the VGA control methods, procedures after the distribution of CRT Chinese characters on the show and other information.
submicron-technology
- IT IS THE TECHNOLOGY TO REDUCE THE SHORT CIRCUIT LEKAGE POWER IN CMOS TECHNOLOGY. BY THIS WE CAN AVOID THE SHORT CIRCUIT POWER
arm6verilog
- arm6 verilog core very good 欢迎下载-arm6 verilog core
vk_par
- VK33XX系列芯片的并口通信程序源代码，可移植-VK33XX series chip parallel communication
QuartusIIerrors
- QuartusII警告信息解析是对QuartusII在使用过程中的常见错误进行了总结。-QuartusII warning analysis is QuartusII in the course of a summary of common errors.
module-signed
- 乘法器例程采用加法器数乘法器实现17位有符号数相乘-On time-multiplier routines the adder on time-multiplier realize number 17 a multiply symbols