资源列表
IIR(vhdl)
- 基于fpga的数字滤波器设计的vhdl源代码-Fpga digital filter design based on the vhdl source code
firshuzilvboqi
- :介绍了基于FPGA的FIR数字滤波器的设计与实现,该设计利用Matlab工具箱设计窗函数计算FIR滤波器系数,并通过VHDL层次化设计方法,同时FPGA与单片机有机结合,采用C51及VHDL语言模块化的设计思想及进行优化编程,有效实现了键盘可设置参数及LCD显示。结果表明此实现结构能进一步完善数据的快速处理和有效控制,提高了设计的灵活性、可靠性和功能的可扩展性。 -: This paper presents FPGA-based FIR digital filter design and
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- Hello Everyone, this site provides useful document to students like me those who are starts doing project in Programming field.
signed_integer_divider_latest.tar
- VERILOG IMPLEMENTATION OF SIGNED INTEGER DIVIDER
atapi_ctl_2_6
- fifo buffer vhdl code
UART
- verilog代码，串口发送接收代码，含有源代码和测试文件，准确可用-verilog code for serial port transmit and receive code, with source code and test files, and accurate available
RTL
- UART 具有rtl ,实验测试可用，已用于实际工程中-UART has rtl, experimental tests are available, it has been used in the actual project
I2C
- I2C 接口的verilog实现源代码，-source of I2C inteference using verilog
CPU
- 多周期cpu结构有特点，性能优良，便于理解。-This cpu is very good.It is easy to understand.
altera_sdram
- Simple SDRAM controller source code for Altera DE2 board
pip
- 好用的视频处理verilog源代码，主要功能是实现picture in picture。-Easy to use video processing verilog source code, the main function is to achieve the picture in. picture.
3
- 利用fpga控制lcd1602的时序，使液晶工作，能够显示字符。-Fpga timing control lcd1602 use to make the LCD work, to display characters.