资源列表
spi
- SPI的Verilog实现(非常的全面和详细，还带有SPI算法的注解)-SPI in Verilog implementation (a very comprehensive and detailed, but also with the SPI algorithm annotation)
I2Cdesign
- Verilog数字系统设计教程【夏宇闻】原书第十章：IIC总线接口模块设计代码包-verilog program for iic bus design. the pakege includes iic protocl master program and behavel slavle program, even includes testbench and data bat files.
WB_I2C
- Routine for I2C in VHDL
i2c_control
- 本文件是iic总线控制器的vhdl语言的源代码程序-2005/09 Bus Controller VHDL language source code procedures
fpga_sec
- 学习使用波形比较功能的基本方法,ModelSim的波形比较的功能可以将当前仿真与一个参考数据（WLF文件）进行比较，比较的结果可以在波形窗口或者列表窗口中查看，也可以将比较的结果生成一个文本文件-Learning to use the wave function of the basic method of comparison, ModelSim wave function can be compared with a reference current simulation (WLF fil
VD-vhdl-Code
- this codes are for convolution encoder and Viterbi decoder synthesis and implementation.
software
- its project for ALtera D2 developement
hh
- 双口RAM的verilog描述 双口RAM的verilog描述-Dual-port RAM of the verilog descr iption of dual-port RAM of the verilog descr iption
ssl_decompose
- SSL安全协议解码源代码，和测试激励文件-SSL security protocol decoder source code, and test incentives document
control_fsm_rtl.vhd
- ALU 有限状态机 ALU 有限状态机 ALU 有限状态机 ALU 有限状态机 ALU 有限状态机-ALU FSMALU FSMALU FSMALU FSMALU FSMALU FSMALU FSMALU FSM
CC2500programmingusingAlteraFPGA
- This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.
Chapter-7
- 练习七在verilog hdl中使用任务（task）319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are program