资源列表
fifo_VHDL
- 该文件是先入先出fifo的源代码和测试文件-the document is first-in-first out fifo the source code and test document
cordicDDS
- Cordic算法实现DDS的Verilog 源码,14位精度，非常实用的。-DDS algorithm Cordic the Verilog source code, 14-bit accuracy, very practical.
FP_ADDER
- This a project of FP_ADDER.-This is a project of FP_ADDER.
VGA-a353
- PROGRAM FILE ...... XILINX ISE DESIGN....2014
vhdl_codes
- this parallel to serial controller-this is parallel to serial controller
sources
- This project is made for DE2 card , that is a chronometer
m68000
- VHDL code for MC68-VHDL code for MC68000
summeri_verilog
- verilog的学习总结，包括自己学习verilog的一些经验-Summary of learning verilog, verilog, including some of their own learning experience
si5324_i2c
- simple I2C module for configuring si5324 to 156.25 MHz clock
drv_dm900
- 这是去年我编写的基于xilinx FPGA的MAC IP 核开发的驱动DM9000的源代码。基于Verilog 语言。-This is the last year I wrote based on xilinx FPGA the MAC IP core developed DM9000 driver source code. Based Verilog language.
zigzag
- 用于FPGA的Z变化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。
nco
- 基于DSP builder搭建的DDS模块，可以用在数字下变频中的NCO等-Based on DSP builder to build the DDS module can be used in digital down-conversion of the NCO, etc.