资源列表
HT16XX
- 利用HT16XX实现段式LCD液晶显示功能 -HT16XX achieved using Segment LCD display
adder
- 实现两个一位二进制数的相加，程序简单易懂，特别适合作为quartus ii的练习-a plus b
zbt_verilog_xilinx
- ZBT SRAM控制器参考设计，ZBT SRAM是一种高速同步SRAM）
fft_2048
- 基于FPGA的2048点的verilog实现-Based on the 2048-point FPGA-verilog to achieve
uart_fifo_cpu_if_sv_testbench_latest.tar
- Serial UART with byte wide register interface for control/status, data, and baud rate.
jpeg_decode_code
- jpeg解码程序，经过验证可用。使用C编程。
buffered-cpu-interfact.tar
- This is a fully synchronous (single clock domain, no asynchronous resets) UART with a FIFO buffered cpu interfact
bcd-7seg
- Create a VHDL code representation of a BCD-to-Seven segment decoder. bcd 7 segment
I8251A
- Verilog 异步串行收发器，收发器的设计，时序状态机的代码编写
pci_core_533
- pci core for pci imlementation
seg_led_rtl
- 使用FPGA控制数码管,在数码管上动态的显示数字,很使用,可以直接作为其他模块的子模块,直接调用-FPGA use of digital control in the digital tube dynamic display figures that use, direct module as other sub-module, called directly
spi_verilog
- 开发语言Verilog,实现spi总线控制，内部有顶层文件，仿真文件等。-Development language Verilog, realize spi bus control, internal top-level file, simulation files.