资源列表
FPGA
- 里面有用NIOS2与SOPC的做的一个串口程序，还有详细文档步骤，对于学习SOPC者有很大帮助-Inside useful NIOS2 to do with the SOPC a serial program, as well as detailed documentation steps, for the study were of great help to SOPC
d1_dec
- d1(BT.656) video decoder VHDL code
ourdev_457422
- Verilog HDL教程包含大量实验例子-Verilog HDL tutorials contain a large number of experimental examples
hdbn_latest.tar
- This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703.
bluespec-80211atransmitter_latest.tar
- This package implements a parameterized baseband hardware logic for an 802.11a Transmitter. This project has since been subsumed by the OFDM baseband project which can also be found on opencores.-This package implements a parameterized baseband har
jiyuchuankoujishu
- 计算机在HDL语言下实现串口技术,UART相关资料-BASIC IN HDL language,chuankou jishu
GAFF
- 伽罗华域GF（q）乘法器设计,完整的源代码。-Galois field GF (q) multiplier design, the complete source code.
sumador
- sumer vhdl code for FPGA of Xilinx
manch
- 该文件是一个完整的工程文件，用VerilogHDL语言编写，包括曼彻斯特编码器的设计文件和仿真测试文件以及解码器的设计文件和仿真测试文件。在Modelsim中仿真测试通过。-The document is a complete project file, with VerilogHDL languages, including the Manchester encoder design documents and simulation test files and decoder design
chuzucheVHDL
- 用VHDL写的出租车计价程序，拥有详细的说明-Taximeter written with VHDL program, has a detailed descr iption of
dig_pll
- 一个简易的数字锁相环，可以产生一个与输入同频同相的输出时钟-A simple digital PLL can generate an input in phase with the same frequency output clock
uart
- RS232控制分频,实现占空比和频率可以控制的分频器-verilog RS232