资源列表
audio_bargraph
- Allows to display an audio bargraph (peak meter and vu meter) of a HD-SD SDI embedded audio signal .
epcs_page_write
- 对FPGA的配置芯片EPCS进行读写操作,由于FPGA内部没有掉电可存储的空间,可肥EPCS当作EEPROM用.-The configuration of the FPGA chip EPCS to read and write operations, there is no power-down may be due to the internal FPGA memory space, EEPROM can be used as a fertilizer EPCS.
washer3
- 洗衣机的Verilog代码，很详细，模块化的，可以借鉴一下-Verilog
spartan3e_picoblaze_timer_LCD
- 基于spartan3e sdk的时钟与LCD实验项目。-Based on spartan3e sdk and LCD clock experiments
Downloads
- clock divider in verilog for FPGA use
Temp1
- rubics cube solver verilog
Temp2
- dice game in verilog
Architecture
- clock divider in XILINX
VHDL
- 1、 输入信号 clk : 时钟（每个象素点的显示时钟） reset : 复位信号 2、 输出信号 vga_hs_control : 行同步 vga_vs_control : 场同步 vga_read_dispaly : 红 vga_green_dispaly : 绿 vga_blue_dispaly : 蓝 3、 技术参数 clk : 24M hs : 30KHZ vs : 57.14HZ -1, input
lpm_ram
- altera LPM_RAM的使用,有简单的程式和模拟结论.大家写的时候可以参考.-altera LPM_RAM the use of a simple programming and simulation findings. we can refer to when writing.
295
- Verilog代码源程序范例，适合初学者借鉴学习-Verilog source code examples for beginners learning to learn
Xilinx_question
- ：ISE5.1i是Xilinx推出的具有ASIC-strength的设计工具，它充分发掘了VirtexⅡPro系列芯片的潜力；Virtex-II Pro 系列芯片的密度是从40,000门到8,000,000门。同4.1i相比，设计人员在编译时所花的时间得到了成倍提高（从100,000/min增加到200,000门/min）并且在器件速度上增加了40 。-: ISE5.1i is a Xilinx introduced a ASIC-strength design tools, which ful