资源列表
16_FIR
- 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
8537553516_FIR
- 滤波器设计最好的例子，采用并行输入方式，具有速度快、滤波能力强的特点。希望通过上传得到大家的认可和评价。-The best example of filter design, parallel input mode, high speed, filter characteristics and strong. We hope the recognition received by uploading and evaluation.
stse2
- Project of tests of FPGA with simulator using ISCAS
ADS8325
- ADS8253，8位串行高速AD转换芯片的FPGA驱动程序，verilog语言版本-ADS8253, 8-bit serial high-speed AD converter chip FPGA driver, verilog language version
1602的FPGA控制
- 利用Altera的FPGA控制1602的模块
1602
- 主要是基于VHDL的1602液晶显示的程序-Mainly based on the 1602 LCD VHDL program
AnEfficientDouble-FilterHardwareArchitectureforH.2
- 在此提出了一種新穎的硬體結構 實時執行的自適應去塊效應 過濾過程中指定的H.264/AVC視頻編碼 標準。-In this paper,a novel hardware architecture for real-time implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard, is presented.The deb
timer
- 用verilog 实现时钟的功能，并在DE2开发板上调试-Clock with verilog and debug on the DE2 board
MAXPPLUS-II
- 这是一个有关使用MAX+PLUS II原理图输入设计方法进行FPGA设计的教程，便于快速入门。-This is about using the MAX+ PLUS II schematic design methodology for FPGA design tutorials, easy Quick Start.
sincos
- 用verilog实现sin和cos的计算-verilog sin cos
1_090220091457
- 基于NiosⅡ的多功能数字相册 竞赛作品 很有参考价值-Nios Ⅱ-based multi-function digital photo album contest of great reference value
89c51
- 利用AT89C51实现LCD日历电子钟源码-AT89C51 realization of the use of electronic LCD calendar clock source