资源列表
bcdflag
- verilog code bcd adder using flag register
code-VHDL
- filter sobel on VHDL
verilog
- VERILOG编程经验总结，对于初学者比较实用，有很多编程技巧及注意事项-VERILOG programming experience, for beginners more practical, there are many programming skills and precautions
ep2c35_5_6_fft_test
- 利用fpga来实现快速傅里叶变换，速度快，稳定，计算精确。-Fpga to implement the use of fast Fourier transform, fast, stable and accurate calculations.
LEDtest
- vhdl 实现fpga 闪灯控制 流水线闪灯 还用signalTAP进行检测，给初学者参考-vhdl fpga flash control lines to achieve flash is also used signalTAP testing, to advanced users
Example-b4-2
- 利用硬件可编程语言VHDL 来实现定制一个8B10B编码器-use VHDL language to 8B10B
lab1
- AXI-Lite bus with SPI on System C
or2000pl
- openrisc200源码，来自open core-Openrisc200 source code,from open core
30S_basketball
- 设计了篮球竞赛30秒计时器。此计时器功能齐全，可以直接清零、启动、暂停和连续以及具有光电报警功能，同时应用了七段数码管来显示时间。此计时器有了启动、暂停和连续功能，可以方便地实现断点计时功能，当计时器递减到零时，会发出光电报警信号。-It designed a 30-second timer basketball competition. This timer functions, can be directly cleared, start, pause, and a row and a ph
apb.v
- AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)
pCApFDpD7pD6
- 分频编码,移位寄存器编码, 分频编码,移位寄存器编码,-shift register
shizhongfinal
- 通过按键控制的数字钟，verilog代码-a diagil clock design by verilog