资源列表
32-bIT-RISC-DOC-a4
- it is 32 bit risc processor code in vhdl
LC3-VHDL-another
- 另一套LC3 CPU VHDL源码及设计文档，对LC3进行了一些取舍和改造，比如NZP改为NZC，更贴近现实CPU硬件架构。按照ASM进行VHDL编码，更适合数字设计初学者学习。
hdlc
- hdlc ip core in communication
VHDL_USERGUIDE
- 本书的主要的服务对象是熟悉硬件系统，而对软件的设计经验缺乏的工程师；叙述了VHDL的用法-This guide is intended for the engineer who is familiar with the principles of hardware design, but has little experience in designing with a language-based synthesis system. It describes the general c
Matlab-IIR
- 数字滤波器是数字信号处理的重要环节，数字滤波器可分为IIR和FIR两大类。本文介绍了IIR和FIR的基本设计原理以及在MATLAB环境下如何利用直接程序设计法、SPTOOL设计法和FDATOOL设计法给出IIR和FIR数字滤波器的设计方法和操作步骤，并给出设计设计实例及运行结果，同时利用MATLAB环境下的仿真软件SIMULINK对所设计的滤波器进行模拟仿真，仿真结果表示设计参数设置合理。-The important aspect of the digital filter is a digit
AVR8051
- 马潮老师的AVR_8051学习板 马潮老师的AVR_8051学习板 --开发工具及软件-- OurAVR_com.htm es_avr_8051_test_board_by_machao_sch.pdf 8051_avr.DDB es_avr_8051_test_board_by_machao_pcb_sch.rar-Ma Chao teachers AVR_8051 learning board
vga_de_v_2
- 实现了机遇verilog的对LCD屏幕工作在DE模式的刷屏方法-Opportunities verilog on the LCD screen work in DE mode refresh
clock
- 自己用Verilog HDL编的一个时钟程序，可以自动计时，设置闹钟，倒计时等功能-a timer programed with Verilog
project_10_first_d1_VGA
- FPGA EP4CE40F23C6 ADV7123 彩条输出源程序，验证可用-FPGA EP4CE40F23C6 ADV7123 color bar output source, verify Available
Manchester_QuartusII
- 完整的曼彻斯特编解码(采用锁相环技术）_QuartusII工程-A complete QuartusII project for Manchester coding and decoding with phase-locked loop technology
verification-guide
- the guide refer to the verilog system to employee the coding in basic and large level
manual
- it explains the basic and imporant vhdl programs. it contains SPICE programs also.