资源列表
ROM_based_sine_wave_generator_VHDL_design
- VHDL基于ROM的正弦波发生器的设计的实验报告，内附源代码-ROM-based sine wave generator VHDL design of experiment reports, included the source code
VHDL_design_of_sequence_detector
- VHDL中序列检测器的设计的实验报告，包括源代码-VHDL in the design of sequence detector test reports, including the source code
7-segment_digital_tube_decoder_design
- VHDL中7段数码管译码器设计与实现的实验报告，包括源代码-VHDL in the 7-segment digital tube decoder design and implementation of the experimental report, including the source code
AMI1
- 本代码是用VERILOG语言描述的AMI码的解码的程序，经过调试是正确的。代码简单易懂。-This code is described in VERILOG language AMI code decoding process, after debugging is correct. Code is easy to understand.
digital_clock
- 用于FPGA可编程逻辑器件的VHDL语言编写的6显示数字钟程序。51单片机驱动6个LED数码管。-Digital clock (VHDL language) for FPGA Development
NIOSII_de2
- 基于SOPC的FPGA系统设计，测试数码管、LED、液晶显示屏，整个系统在DE2上运行通过，使用的是Quartus 6.1套件-FPGA-based SOPC system design, testing, digital tube, LED, LCD display, the entire system run by the DE2, using Quartus 6.1 Suite
usb_xilinx_vhdl
- usb开发代码 基于VHDL语言的FPGA-usb development of VHDL-based FPGA code
pwm
- 采用vhdl语言实现12路的pwm波控制。-Language implementation using vhdl wave pwm control of the road 12.
VHDL
- 本文从最基础的VHDL语言组成开始详细的介绍VHDL语言的应用。-In this paper, the composition of the most basic VHDL language began to detail the application of VHDL language.
8bitadder10.3.6
- 8bit加法程序,应用VHDL语言编写，可用于FPGA开发用-8bitadder
a_vhdl_8253_timer_latest.tar
- 一个用VHDL语言编写的8254定时器。具有一个同步处理器接口比异步的INTEL8254要好-A VHDL 8254 timer，uses a synchronous (Wishbone) processor interface, rather than an asynchronous of the Intel 8254.
cf_fft_latest.tar
- 整个设计使用了流水线设计，运用了同步的使能和复位信号。这是一个4k点的fft。实部和虚部均为18bit，总共为36bit精度。-All designs are pipelined with a synchronous enable and reset. 18 bit precision, real and imaginary. Total is 36 bits.