资源列表
fifo
- 本程序主要实现对先入先出功能模块的程序编写- This procedure is mainly to achieve the FIFO function module programming
Mars_EP1C6F_Comprehansive_demo(VHDL)
- FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。综合实验的源码。包括交通灯实验等。-FPGA development board support VHDL code. Chips for the Mars EP1C6F. General experimental source. Experiments, including traffic lights.
Mars-EP1C6-F_code3
- 此包为FPGA学习板的综合实验程序源代码,包括两个实验:交通灯和数字时钟.-This packet FPGA board to study a comprehensive experimental program source code, including two experiments: the traffic lights and digital clock.
seven_segment1
- vhdl code for 7 segment
serial_adda
- 串行AD/DA的实验。Verilog初学者实验程序。已在quartus下测试成功。-Serial AD/DA experiments. Verilog beginners experimental procedures. Been in quartus under test success.
CY7c68013
- CY7c68013的读写程序,开发环境是ISE-CY7c68013 write and read program
Memoria
- Circuito que implementa el uso de memoria nvram de la tarjeta nexxys 2 en vhdl
PLL
- PLL 时钟模块 Quartus II平台的简单设计实例 附仿真波形
bubblesort
- 实现串入数据的排序，并在QUARTUS ii 上仿真过-To achieve the sort string into data and QUARTUS ii emulation over
uartfifo
- 用 Verilog语言编写的串口发送接收程序，带FIFO 已调试通过-Verilog language with sending and receiving serial program with debugging through the FIFO
serial_adda
- 实现串口，在ISE8.2运行，芯片为xinlix的virtex4-To achieve serial port, ISE8.2 running chip for xinlix the virtex4
Verilog-max538
- verilog编写的max538程序模块-verilog for max538