资源列表
statemachine
- 自己做的一个关于more状态机的三种描述的比较。以后会有更多的资料，请大家关注。-doing more of a state machine on the three described earlier. Many more information, please everyone's attention.
clock_CPLD
- 采用MaxPlusII写的一个小时钟程序，也是供初学参考。呵呵。注///版主，开发环境里面没有MaxPlusII.-MaxPlusII used to write a small clock procedures, as well as reference for beginners. Ha ha. Note / / / moderator, development environment there's no MaxPlusII.
TP1_ALU
- Unité arithmetique et logique Nexys 2 board
rom_modelsim
- modelsim仿真中关于rom的初始化处理方法。内附文档讲解仿真的详细过程以及必备的文件。
4.1
- VHDL学习的基础教程，是eda技术使用教程的第四章节知识总结。-VHDL Tutorial learning is the use of EDA technology tutorial summary of the fourth chapter of knowledge.
TIMER
- 这个为倒计时时钟显示控制实验例子程序，大家可以参考-The countdown clock shows control experiments for the example program, we can refer to
tdm_latest[1]
- TDM，就是时分复用。本程序完成4通道，没通道最多32路64K信号的交换，就是说可以完成32x4个电话信号交换-TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange
rx_tx_module
- 使用altera公司的处理器，使用verilog语言编程，程序功能是窗口发送接收程序-Use altera' s processors, using verilog language programming, the program features a window sending and receiving procedures
f50k
- VHDL产生时钟50分频程序，供初学者参考-VHDL generated clock frequency of 50 procedures, the reference for beginners
decoder
- 基本门电路和译码器试验，含quartus8.0工程，源码，仿真和详细操作步骤，适合初学者上手。-Basic gate circuit and decoder tests, including quartus8.0 engineering, source code, simulation and detailed steps for beginners to get started.
pine_line_adder8
- 8 位全加器的设计，采用多pipeline设计方法-8 full adder multi-pipeline design
DDS-frequency-synthesizer
- 本文主要讨论了Verilog语言的基于DDS的波形发生器的设计。从设计要求入手，本文给出了DDS的详细设计过程，包括各个模块的设计思想，电路图，Verilog语言程序代码。其大致思想为通过频率控制字和相位控制字去控制正弦函数的ROM存储表的地址并对应着得到其幅度值，最终达到输出需要波形的目的。-This paper mainly discusses the design of the Verilog language, the DDS-based waveform generator. Star