资源列表
SUB_Float_IEEE_754
- IEEE754 floating point sub
vga_controller_vhdl
- Source code files for vga written in VHDL,Easy to understand for those who havent done Fpga Vga interfacing-Source code files for vga written in VHDL,Easy to understand for those who havent done Fpga Vga interfacing
pingpang
- FIFO读写，用使用状态机完成两片FIFO读写，乒乓操作。-FIFO read and write, using the state machine complete with two FIFO read and write, ping-pong operation.
UpDownCounter_FSM
- This code is an Up Down Counter in FSM using Verilog HDL.
firmatlab
- fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
CPU
- 以前在学校里的课程设计，使用verilog编写的一个CPU程序，可以下板子
SERIALADDER
- SERIAL ADDER 8-BIT-SERIAL ADDER 8-BIT
LCD12864(st7920)
- 整理的网上关于LCD12864(ST7920控制器）的串并口程序，已在stc89c52rd+11.0592MHz的情况下测试通过-Finishing line on LCD12864 (ST7920 controller) serial and parallel programs, in the case of stc89c52rd+11.0592 MHz test
IQ_SIGNAL_GENERATION_CODE
- IQ信号发生器_好用_测试正确,项目已经使用-IQ signal generator _ with _ test correctly
eep
- 实现了基于SPI接口的EEPROM控制器功能-SPI-based EEPROM controller
hamming.tar
- Verilog语言实现的Hamming(3,7)编码器，可用于FPGA实现
niosHAL
- 这是nios里面的hal所有的库函数的介绍，很实用，再编写nios IDE是帮助很大。-This is the nios hal inside the introduction all the library functions, it is practical, and then write nios IDE is a great help.