资源列表
Codes
- USB 2.0 using VHDL with files : main.c, drice.c and HIGH_SPEED_USB_CORE_SETUP_TRANSACTION
vga3_you
- VGA接口应用的VHDL语言编程， 已经通过实验验证-VGA interface application has been verified by experiment. . . . . . . . . . .
11053022286676
- 基于 MATLAB/DSP Builder DSP 可控正弦信号发生器设计-MATLAB/DSP Builder DSP controlled sinusoidal signal generator design
modelsim-book
- modelsim仿真教程，教你如何使用modelsim的简明教程。-modelsim simulation tutorial to teach you how to use a simple tutorial modelsim.
ASS2_bench
- Verilog HDL for IRDA transmitter by DE2 board using Altera Cyclone II Quartus-Verilog HDL for IRDA transmitter by DE2 board using Altera Cyclone II QuartusII
led_state3
- verilog 三段式LED,有益于参考学习状态机！-verilog led three state
async_fifo-and-verilog
- 异步fifo的详细原理分析说明及verilog源代码，经典推荐！-Detailed descr iption of the principles and analysis of asynchronous fifo verilog source code, the classic recommendation!
DE2_NET
- Altera的DE2开发板上关于DM9000A的Demo，做好的IP核，在Nios II下运行-Altera s DE2 development board Demo about DM9000A, include IP core, and running under Nios II
spi_test
- vhdl实现spi对M25P80flash进行操作。-vhdl realize spi on M25P80flash operation.
qiangdaqi
- 基于verilog语言的六路抢答器设计代码，编译环境为quartus9.0，自己的一个课程设计，测试可用-Based on the six-way Responder design code verilog language compiler environment quartus9.0, one of their own curriculum design, test available
clkdiv
- 《深入浅出玩转FPGA学习课程特权同学——实验代码》时钟分频-The students easily understood how to play the FPGA courses privilege- experimental code clock frequency division
Txd
- 1000M以太网媒体介入控制器EMAC的传输部分的源代码-1000M ethnet transmiter