资源列表
vdlcode
- learn about vhdl to implement for basic ckts-learn about learn about vhdl to implement for basic ckts
murty-vhdl
- these files are help full to develop vhdl codes
murty-vdl1
- these are basic vhdl codes to further improvement
bitdetect
- verilog代码编写110100序列的序列检测器，用状态机实现，包括仿真测试代码-verilog coding sequence detector 110100 sequence state machine implementation, including simulation test code
Programmable-source
- 可编程源代码，基于Verilog的程序，西电2013秋学期最新版上课要求自编的程序，txt文件-Programmable source code, Verilog-based program, Western Electric 2013 autumn semester class requires the latest version of the program self
verilog-hdl
- VHDL的各种算法算例，可供西电的大作业设计参考，是学习可编程语言的必备算例-VHDL examples of various algorithms available for Western Electric' s big job reference design is essential to learn a programming language examples
finaldesign_watch
- 基于VHDL的数字跑表源码，芯片采用ALTERA公司的ACEX1K 系列的EP1K10TC100-3，项目设计过程中，用EDA技术作开发手段，运用VHDL语言，实现从0.01秒到59分59秒59 的设计。-VHDL-based digital stopwatch source, ALTERA chip company ACEX1K series EP1K10TC100-3, the project design process, by means of EDA technology for th
a
- 三人表决器，但拨开两个及其以上开关时，Led就会亮起，只有一个开关时，灯不亮-Three of the vote, but poke two and above switch, Led will light up when there is only one switch, the light does not shine
61IC_S4656
- stm32与FPGA的通讯总线FMSC，非常的实用-stm32 and FPGA communication bus FMSC
IIC_and_usartPC
- fpga的IIC与USART串口verilog代码，非常实用-The IIC and USART serial fpga verilog code, test
exp10.vhd
- 这是一个基于FPGA的可调脉冲发生器的程序，可以实现周期和占空比的调节-This is an adjustable pulse generator based on FPGA program, you can adjust the duty cycle and achieve
3
- 可容纳6组参赛的数字式抢答器，每组设一个按钮，供抢答使用。 抢答器具有第一信号鉴别和锁存功能，使除第一抢答者外的按钮不起作用。 设置一个主持人“复位”按钮。 主持人复位后，开始抢答，第一信号鉴别锁存电路得到信号后，有指示灯显示抢答组别，扬声器发出2~3秒的音响。 计分，每组开始预置100分，由主持人记分，答对一次加10分，答错一次减10分。-Smart Responder