资源列表
ddr-sdram--chengxu
- ddr的控制程序，实用Verilog语言实现的非常的具体，非常无奈过的实用。-ddr
DDR_controller_verilog
- ddr的控制程序，用verilog实现的，非常的具体。-ddr
rotate_switch
- 双触点旋转开关verilog驱动，内置消抖模块。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-Double-contact rotary switch verilog drive, built-in modules eliminate shaking. Prepared source files using the emacs, iverilog simulation adopted, within the simulation images png screen
jitter_eliminate
- verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-verilog descr iption of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted
trigger
- D触发器和JK触发器，使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-D flip-flop and JK flip-flop, use emacs to prepare source file, iverilog simulation adopted, within the simulation images png screenshots
freq_divider
- 8bit分频器，最高256*2=512 分频，使用emacs编写源文件，iverilog仿真通过-8bit divider, the maximum 256* 2 = 512 min frequency, use emacs to prepare source file, iverilog simulation success
cfft
- 用verilog语言编写的基4FFT，采用CORDIC算法实现的，仿真过，结果很好！-I use verilog language to design a FFT base 4,and use CORDIC arithmetic to achieve this. last , I test it, it looks very good
SFIFO
- 可以实现任意位的同步FIFO的verilog实现-the verilog code of a common SFIFO
SCRAMBLER
- 32位扰码器的verilog代码，编译通过-The Verilog code of 32_bit scrambler
sheji
- 本科毕设，基于cpld的光栅信号处理，包含源代码和模块框图-Undergraduate Bi is located, based on cpld grating signal processing, including source code and block diagram
cout60
- 用VHDL语言编写的60进制计数器，初学者使用-VHDL language with the 60 binary counter, for beginners to use
DDR_SDRAM
- DDR——SDRAM学习资料，DDR——SDRAM学习资料-DDR- SDRAM learning materials, DDR- SDRAM learning materials