资源列表
recover
- VHDL设计的HDB3的译码器，采用了四位移位寄存器来判断之前码元1/0，造成输出有5位时延。-VHDL design of HDB3 decoder, using four yards before the shift register to determine the yuan 1/0, resulting in output has five delay.
VHDLcoding
- 本文件时VHDL的各种编写规范，有助于开发者在平时养成好的编码习惯-This document, the various write VHDL specification, helps developers to develop good coding habits in peacetime
1a_DesignOverview
- Basic acknowleage of System Verilog, an presentation from acellera. Basic acknowleage of System Verilog, an presentation from acellera. -Basic acknowleage of System Verilog, an presentation from acellera.Basic acknowleage of System Verilog, an presen
VGA_Shell
- this the file that functioning the VGA controller ... and it is workable-this is the file that functioning the VGA controller ... and it is workable..
4bitlock
- 本文以在PFGA芯片中实现一个简单的可控正弦信号发生模块的设计为例，详细介绍DSP Builder的使用方法，从而有介绍一种另外PFGA—DSP算法的程序方法。-In this paper, in the PFGA chip to achieve a simple sinusoidal signal control module design as an example, detailing the use of DSP Builder methods, thus introducing a k
ahb_system_generator_latest.tar
- this project relates ahb
MAC_MPEG2_AV
- MAC mpeg hardware code zip
MAC_MP3_Hardware
- MPeg audio encoder/decoder codes
burstpage
- SDRAM控制器在FPGA实现源代码，能实现burst传输-SDRAM controller in FPGA realization of the source code, can achieve burst transfer
RTL
- 用VHDL实现求两个数的最大公因数。数据路径和控制路径。-Seeking to use VHDL to achieve the greatest common factor of two numbers. Data path and control path.
vhdl_practical_manual
- VHDL使用教程, 怎样编写高效率的vHDL设计-VHDL practical user manual