资源列表
project3_1
- 逐次进位加法器，HDl verilog语言编写，能在DE2上运行-Successive carry adder, HDl verilog language, able to run on the DE2
project4_1
- D触发器门级实现，有异步复位置位，HDl verilog语言编写，能在DE2上运行-D flip-flop gate-level implementation, there are asynchronous Reset_Set, HDl verilog language, able to run on the DE2
go-to-the-digital-world-of-FPGA
- 走进FPGA的数字世界，让我们更浅显易懂的了解FPGA，了解数字。-FPGA into the digital world, so that we are more easy to understand to understand FPGA, to understand numbers.
fpga
- 自己写的一个基于quartus ii12.0的一个建立工程及通过modelsim仿真的一个图文教程。提供大家参考。-To write a quartus ii12.0-based engineering and through establishment of a modelsim simulation of a graphic tutorial. Provide your reference.
source
- 多个verilog的基础例子，初学verilog者必备，里面包含源文件及pdf文件的总述。-The basis of several verilog examples of the essential beginner verilog, which contains the source files and pdf files Overview.
lab1_1
- 简单的PARWAN移位寄存器实验 移位寄存器的设计与仿真 -PARWAN shift register shift register Experimental Design and Simulation
hdlc
- 基于FPGA的hdlc协议控制器的实现，用vhdl语言编写。-FPGA-based implementation of hdlc protocol controller, using vhdl language.
7series_hdl
- Xilinx 7 Series HDL Coding Recommendations. Very useful for Xilinx FPGA design.
7series_scm
- Xilinx 7 Series Device Primitive Cells. Very useful for Xilinx FPGA design.
pwm_task_logic
- 脉冲宽度调节（pwm）的verilog源码-Pulse width modulation (pwm) the verilog source
cam
- 经过ModelSim验证过的cam程序，基于VHDL语言编写-After ModelSim verified cam program, based on VHDL language
test_proiect_MCeas
- test m ceas. este un ceas. ceasul are minute ore secunte.