资源列表
FIR
- 基于fpga的FIR滤波器设计,已通过modesim仿真结果正确,verilog编写-Fpga-based FIR filter design, has passed modesim simulation results are correct, verilog prepared
9280-
- 基于FPGA的AD9820芯片转换程序,采用verilog编写,成功通过仿真-The AD9820 chip FPGA-based conversion process, using verilog prepared successfully through the simulation
CH372
- 基于fpga的USB控制器，采用CH376芯片，verilog代码编写，通过仿真-Fpga-based USB controller, using CH376 chip, verilog code prepared by simulation
hsk4571_clock
- 数字时钟 VHDL实现，可调节时分秒，在QUATTUS||9.0下编写，可在9.0及以上版本运行并下载，芯片为Altera的Cyclone3 EP3C8T1-Digital clock VHDL realization, minutes and seconds can be adjusted in QUATTUS | | 9.0 under preparation, can be run in the 9.0 and above versions and download, chips for
hsk4571_cuankou
- 串口通信SCI VHDL实现，在QUATTUS||9.0下编写，可在9.0及以上版本运行并下载，芯片为Altera的Cyclone3 EP3C8T1-Serial communication SCI VHDL realize, in QUATTUS | | 9.0 under preparation, can be run in the 9.0 and above versions and download, chips for Altera' s Cyclone3 EP3C8T144
hsk4571_sgna_generator
- 信号发生器的VHDL实现，可调节波形及频率，方波、锯齿波、三角波等，在QUATTUS||9.0下编写，可在9.0及以上版本运行并下载，芯片为Altera的Cyclone3 EP3C8T1-Signal Generator VHDL implementation, adjustable waveform and frequency, square wave, sawtooth, triangle, etc., in QUATTUS | | 9.0 under preparation, can be
VHDL
- 数字电路实验程序代码打包下载 版本 宁波大学学年数字电路实验 VHDl编程 部分 -Digital circuit experiment program code package download version Ningbo University academic year programming section VHDl digital circuit experiment
FPGA-
- FPGA实现串行接口 RS232,包括RS232是怎样工作的，如何产生需要的波特率，发送模块，接收模块，应用实例-FPGA Implementation of serial interface RS232, RS232, including how it works, how to produce the desired baud rate, transmit module, receiver module, application examples
fpga_nes-master
- 这是一个完整的红白机nes游戏fpga实现，经测试可用，使用ise14.1以上版本的工程文件，开发板使用的是xilinx spartan6-This is a complete NES nes games fpga implementation, the test is available, use ise14.1 above version of the project file, the development board using xilinx spartan6
NOIS-II_AES
- 基于NOIS II的AES加解密系统 完整的工程文件 -NOIS II-based AES encryption and decryption of a complete project file system
project2_1
- 3:8译码器，HDl verilog语言编写，能在DE2上运行-3:8 decoder, HDl verilog language, able to run on the DE2
project2_2
- 7段译码管，用于显示数字，HDl verilog语言编写，能在DE2上运行-7 segment decoder tube used to display numbers, HDl verilog language, can be run on the DE2