资源列表
Experiment01
- 在这一个实验，我们要以上图作为基础，建立一个并行操作的流水灯模块-In this experiment, we have to figure above as a basis for establishing a parallel operation of the water lamp module
adder
- VHDL Adder implementation done in FPGA environment. VHDL Adder implementation done in FPGA environment.-VHDL Adder implementation done in FPGA environment.VHDL Adder implementation done in FPGA environment.VHDL Adder implementation done in FPGA envir
Experiment02
- 闪耀灯和流水灯,闪耀频率是指一个LED开和关的周期时间。实验二中的flash_module所制定的输出如 上。-Sparkling lights and water lights, LED flashing frequency is an on and off cycle time. Experiment II enacted in flash_module output above.
Experiment03
- 消抖模块之一，一但检测到按键资源按下（高电平到低电平变化），“电平检查模块”-Debounce one of the modules, but detected a key resource pressed (high to low change), " level check module"
Experiment11
- SOS信号,首先我们先要建立功能拟似S函数和O函数的功能模块。-SOS signal, first we need to establish functional quasi S-function, and O function modules.
t_encoder
- encoder file with VHDL code, encoder file with VHDL code e ncoder file with VHDL code-encoder file with VHDL code, encoder file with VHDL code encoder file with VHDL code encoder file with VHDL code
Experiment08
- 实 验 八 是PS2解 码 模 块。 然 而 笔 者 在 设 计 上 ， 对ps2_detect_module.v 添 加 了 PS2_Done_Sig,这个信号无疑是表示了“一次性操作”-Experimental Eighth PS2 decoding module. However, the author designed the ps2_detect_module.v added PS2_Done_Sig, this signal is undoubtedly represents &
rc_adder
- Ripple carry adder program written in VHDL
Johnson_count
- Johnson count in V tested ok Johnson count in V tested ok-Johnson count in V tested ok Johnson count in V tested ok
Johnson_count_dft
- DFT code for johnson count written in V
ofdm4
- 16QAM加上IFFT调制的OFDM的VHDL的代码，编译通过，可以拿去仿真借鉴-Plus IFFT OFDM 16QAM modulation of the VHDL code, compile, you can take the simulation draw
VGA_FPGA_v8_08
- VGA0808矩阵FPGA代码（Verilog HDL语言）-VGA0808 matrix FPGA code (Verilog HDL language)