资源列表
VHDL 编程
- 包含源代码
gameksinghua
- 清华大学实验箱自带实验程序，对于编程参考很有益．-Tsinghua Experimental me own experimental procedures, the reference is very useful for programming.
Tutorialvhdl
- TUTORIAL VHDL spanish
LCD_ML605
- Motor speed controller using VHDL
LCD_Driver_better
- this a characteristic 16x2 LCD Driver by VHDL-this is a characteristic 16x2 LCD Driver by VHDL
cordiccos
- cordic算法的fpga的实现 采用altera芯片-cordic realization algorithm using fpga chip altera
Encoder-Frequency-Doubling-
- 对主轴编码器脉冲固定倍频，首先4倍频，然后N倍频，要求转速波动小,内附参考资料-Fixed on the spindle encoder pulse frequency, the first 4x, then N frequency, requiring speed fluctuation is small, containing a reference
asd
- FPGA数字移相器,编程环境为QUIRTE2,编程语言采用硬件描述语言vhdl-FPGA Digital Phase Shifter, programming environment for QUIRTE2. programming language used VHDL hardware descr iption language
CacheFromScratchFinalWeek_ise12migration
- VHDL implementation of an 8-bit multilevel cache. Produces timing diagrams when run on a suitable IDE such as Xilinx.
CPU
- 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware descr iption language developm
cordic_verilogfiles
- Design of FFT on FPGA using VHDL
digital_clock
- verilog digital clock.四位 有计时器 有秒表 。是学生作业。 原创。 适合初步学习verilog的学生。 -verilog digital clock/4 bits/ up_down/stopwatch