资源列表
tut_quartus_intro_verilog
- introduction about verilog
EDA-clock
- 基于FPGA的时钟设计,主要能实现计时和日历功能-The clock design based on FPGA, the main can realize clock and calendar function
1(2)
- 署名FPGAexpress_intr介绍的一本好书-FPGAexpress_intr
DDS
- 基于ＦＰＧＡ平台，实现了直接数字频率合成。
61EDA_D944
- 抢答器的实现，主要通过vhdl语言，并有原理图-Answer s achieved, primarily through the VHDL language, and schematic
xge_mac_latest.tar
- Ethernet 10GE MAC 以太网10G的MAC Verilog代码实现-Ethernet 10GE MAC
state_machine
- verilog编程状态机实战训练：1.本实例通过实现一个状态机来控制8个LED循环闪亮； 2. 工程在project文件夹里面； 3. 源文件和管脚分配在rtl文件夹里面； 4. 下载文件在download文件夹里面。-verilog programming state machine combat training: 1. This example by implementing a state machine to control 8 LED flashing cycle 2
51645465
- verilog VGA 显示的参考资料，有助于迅速掌握FPGA的VGA接口技术-verilog VGA display reference information that helps to grasp the technology of FPGA VGA interface
Matrixkeyboarddisplaycircuit
- Matrix keyboard display circuit
dds
- 做的一个DDS,用quartus仿真成功-Do a DDS, a successful simulation with quartus
I2C-SourceCode
- I2C Inter Integrated Circuit Master Controller SourceCode
FSM_3
- Final state machine written on VHDL in Quartus II. Imple. Implements the working principle of a sensor which detect the spinning direction (e.g. a motor) and depending on the direction a DuplexCounter is set to "up" or "down" mode.