资源列表
uart16450
- uart 16450合集,xilin altera lattice-collection of uart controller 16450
vgaxianshi
- 基于Verilog语言是VGA显示电路设计文件、顶层设计文件-Based on Verilog language VGA display circuit design file, the top-level design file
serialports2
- 使用verilog以及VHDL编写的将串口数据转换为32位并口数据，作为FPGA和DSP接口使用（DSP型号：6205）-Use verilog and VHDL will be prepared by a 32-bit serial data into parallel data, as the FPGA, and DSP interface (DSP Model: 6205)
Verilog
- 基于Quartus2的Verilog实例详解-Detailed examples of Verilog-based Quartus2
an181_2_2
- Excalibur FPGA多主参考设计-Excalibur Solutions— Multi-Master Reference Design
buzz_ise9migration
- TISH PROGRAM VHDL CODE -THHIS CODE GOD FOR DRIVE BUZER IN ISE
232543
- FPGA Implementation of QFT based Controller for a Buck type DC-DC Power Converter and Comparison with Fractional and Integral Order PID Controllers
13-traffic
- 这是一个成功的交通灯VHDL和Verilog源代码，已在DH－33001开发板上调试成功。-This is a successful traffic lights VHDL and Verilog source code, in the DH-33 001 development board debugging.
BISHE
- VHDL程序，关于暖气片的自动控制，非常有用-VHDL program, with regard to the automatic control of radiators, very useful
shuzibiao
- xilinx下使用vhdl编写数字表 具有启动、复位、暂停、暂停后继续计时等功能 能显示的秒计数时间精确到小数点后第二位，即能显示**.**s -xilinx vhdl prepared using digital watch with a start, reset, pause, pause, continue after the timer function can display the seconds counting time accurate to the second
piano
- piano musical con la 5 octava
S3DSP_PS2_LCD_TEST
- FPGA LCD test code in VHDL.