资源列表
timeforsopcbuider
- NIOS II IDE 编程， 定时器测试程序，仅供参考。-NIOS II IDE programming timer testing procedures, for information purposes only.
modelsim
- 一个用于modelsim软件的激活的license，放置于相应的安装目录下即可-this is a license for modelsim Software
gates1_nik
- this are simple vhdl gates
FPGA
- 在FPGA_MarkIII_2C8_2基础上，接口使能的基础上，做的测试,检验指定BlockNo块的好坏.-In FPGA_MarkIII_2C8_2 based on the interface is enabled on the basis of doing testing, inspection specified BlockNo block is good or bad.
gongcehngsheji_477-2
- 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
turbo_encode
- turbo码的编码程序,verilog HDL,在ISE环境中-turbo code encoding process
verilog
- BASIC VERILOG CODES -BASIC VERILOG CODES ..
VGA_interface_drive_program
- VGA接口的显示屏驱动程序，可显示小绿人-VGA interface display driver, can show little green men
jishuqi
- 计步器程序 使用vhdl描述 实现实时的计步功能 用fpga实现已通过-step counter Pedometer programs use VHDL achieve real-time project described in step function already through fpga realizing
kb-test
- this a test keyboard code -this is a test keyboard code
nandflash
- i am very handsome and very clever
vhdl--timer
- 关于基于fpga的，数字化时钟vhdl实现源程序，推荐大家下载仿真实现。