资源列表
hdlc
- 基于FPGA的hdlc协议控制器的实现，用vhdl语言编写。-FPGA-based implementation of hdlc protocol controller, using vhdl language.
XillinxFor_CKJH
- 程控交换机芯片用的VHDL语言程序, 与DSP配合完成程控交换机功能-VHDL code for tele-communication switcher in education
crc_verilog_xilinx
- 各类CRC效验码 有CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8-CONTAIN CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8
cnttest
- this is counter vhdl code.
ps2_Code
- ps2接口编程实验，采用VHDL编程，用ISE开发工具-ps2 interface programming experiments using VHDL programming, development tools with ISE
sha1_v01
- 基于FIPS 180-4标准的SHA-1算法的verilog HDL实现，分模块分别实现-FIPS 180-4 standard SHA-1 algorithm-based verilog HDL sub-modules, respectively, to achieve
verilogdiv_3_5_7
- verilog写的奇数分频，适合初学的同学分析，容易上手，已测试。-verilog to write the odd divider, suitable for beginner students, easy to use, have been tested.
v5gtp_sdi_drp_control
- xilinx virtex5 sdi drp 控制-xilinx virtex5 sdi drp control
NANDFlashcontrolandFIFOcontrol
- 实现NAND Flash块的控制存取以及同步的FIFO的控制 verilog 代码-NAND Flash control access and control of the synchronous FIFO verilog code
2
- 设计一个可容纳四组参赛者同时抢答的数字抢答器，可判断第一抢答者并报警指示抢答成功，其他组抢答均无效。若提前抢答则对相应的抢答组发出警报。同时还具有计分功能，若抢答成功并回答正确增加1分，答错不扣分。- Designed to accommodate a four contestants answer in the same time the number of Responder, First Responder who can determine the answer in the suc
DDS
- FPGA，基于VHDL语言，用于ROM查找表的方式，实现DDS，能够输出正弦，方波，锯齿波，方波四种波形，可以改变幅值和频率。-DDS based on FPGA(VHDL)
RISC_CPU
- 一个简单CPU设计，可以让读者在计算机组成原理和verilog语言方面受益-A simple CPU design, allows the reader to the computer principles and Verilog language benefit