资源列表
cal_verilog
- 计算器芯片的verilog实现代码！ 时序仿真成功-calculator chips to achieve the Verilog code! Timing simulation success
ss_pcm
- It was tested on a XESS XCV800 board interfacing to a proprietary device with a TI DSP, exchanging PCM streams in both directions.
AD
- 利用FPGA芯片控制模拟信号到数字信号的转换-FPGA chip to control the conversion of analog signals to digital signals
clock_VHDl
- 一个初学者写的时钟程序，VHDL语言，MAXPLUS环境。
organ
- Altera QUARTUS 7.2的矩阵键盘电子琴完整工程（含源码），在EP2C20芯片上实现-Altera QUARTUS 7.2 Project of matrix keyboard electronic organ, implement on EP2C20 chip.
PCI_5Vjinshouzhi
- PCI通用金手指的定义和说明，还有不同金手指的说明-The definition and descr iption of the PCI Universal Goldfinger, there are different Goldfinger instructions
chap3
- verilog, please download and excise-verilog,please download and excise
frequencycounter
- 频率计介绍了用VHDL语言编写的频率计的程序，详细编写了如何测频，如何计数频率。
DCT2
- 2 维 DCT的VHDL实现以及 测试代码 ， -2-D DCT of the VHDL implementation and test code
9363
- AD9363控制接口,在TDD模式下，cmos接口传输数据，数据率61.44MHz，时钟122.88MHz-ad9363 interface.tdd mode.
code
- cpld 实现8253的功能,做计数、测速可以参考- cpld achieve 8253
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider