资源列表
filter
- 巴特沃斯滤波器的Verilog实现，基于matlab-Butterworth filter Verilog implementation based on matlab
vspi
- 通用异步串行通信协议 SPI模块 VHLD语言 -SPI module
music
- 是用VHDL语言编写的乐曲演奏程序，详细的写了各个模块的子程序-VHDL language is the music playing program
DCT
- dct for verilog useful
subtraction
- 基于FPGA的VERILOG语言的四联十六进制的减法程序-Based on quadruple hexadecimal subtraction process of FPGA VERILOG language
watch
- 数字钟，简单的数电应用，电子表源程序，常用也使用-watch
rtl8029source.rar
- 8 位单片机与以太网控制器 RTL8029 接口的VHDL 设计,8-bit Microcontroller with Ethernet Controller RTL8029 Interface VHDL design
jicunqi
- 寄存器的VHDL实现，寄存一组二值代码，对寄存器的触发器只要求它们具有置1、置0的功能，在CP正跳沿前接受输入信号，正跳沿时触发翻转，正跳沿后输入即被封锁。-Register VHDL implementation, hosting a group of binary code, on the flip-flop registers only requires that they have set one, set 0 functions in CP are dancing along the
vspi
- 一个用vhdl语言写的spi接口实例，经过altera的fpga测试可以使用。-Written in a language with vhdl spi interface to an instance, after the fpga altera test can be used.
Subway_VHDL
- 模拟地铁自动售票机选票、付款、取票、找零等功能，包含软件仿真和硬件响应，可供仿真测试和FPGA验证。-Analog subway ticket vending machine ballots, payment, tickets, give change and other features, including software simulation and hardware response for simulation and FPGA verification test.
ch3ex
- 部分组合逻辑数字电路的VHDL代码，包含必要的功能描述-Some combinational logic digital circuits VHDL code, containing the necessary functional descr iption
hidoh
- 汇编计数器，可以在计算机上直接运行的软件程序-Compilation of the counter, you can run directly on a computer software program