资源列表
cpusimple
- a simple vhdl of cpu
NCLPROJECT
- The main objective of the project is to reduce the complexity of the digital circuit with improvement in performance. Two versions of a reconfi gurable logic element are implemented one without extra embedded registration and the other with extr
ninek468c
- 基于FPGA的IP模块程序，包括数字输入输出控制，寄存器控制和访问-IP MODULE
FPGA-adpter
- FPGA实现网卡的收发基本功能，满足网络通信需求-FPGA adpter
fifo
- 很多关于FIFO的文章其实讨论的都是空/满标志的不同算法问题。 在Vijay A. Nebhrajani的《异步FIFO结构》一文中，作者提出了两个关于FIFO空/满标志的算法。 -FIFO FULL/EMPTY Arithmetic
usb_Phy
- usb1.1 VHDL源码，主要描述收发数据过程-usb1.1 the VHDL source code, descr iption of the send and receive data process
FPGA
- 本人常用的FPGA程序，拿出来跟大家分享一下，希望对大家有用！-I used the FPGA program out to share with you, want to be useful!
modelsim-run-one-step--Error-
- 用modesim仿真的时候会出现只运行了一步就不动了，显示"# ** Error: (vsim-3601) Iteration limit reached at time 0 ps."的解决方法。-With modesim simulation run only when there will be a step not move, display " #** Error: (vsim-3601) Iteration limit reached at time 0 ps." S
12864VHDL
- 采用VHDL语言编写的程序让FPGA驱动12864显示作图和划线。-Using a program written in VHDL to FPGA mapping and marking display driver 12864.
vga_card
- VGA模块的VHDL代码和软件驱动，可作为外设挂接在Avalon总线上。用一块SRAM作为显存，双缓存切换模式。-VGA module VHDL code and software drivers can be articulated as a peripheral bus in Avalon. As with a piece of SRAM memory, dual-mode cache switching.
RC_Engine
- 用Verilog實現的推薦系統, 用於片上系統設計-It is the Verilog source code for recommendation system. It can be used in SoC design.
herisong
- untuk fuzzy logic program