资源列表
VHDL5
- 加法器 乘法器电路 除法器电路设计 键盘扫描电路设计 显示电路-Adder multiplier circuit divider circuit design keyboard scan circuit design show circuit, etc.
ram32
- 并行RAM程序，2位并行读取，可以参考用于要求高速缓存的设计。-Parallel RAM program, two parallel reading, you can refer to the cache for the required design.
hash_function_sha3
- The synthesis software is Xilinx ISE version 14.4. The low throughput core has been synthesized targeting a very cheap Spartan 3 (XC3S5000-4FG900). This project is licensed under the Apache License, version 2. I prefered on the internet
EDA
- VHDL实现一个整点报时的秒表第一个子程序-VHDL achieve a integral point time of the stopwatch 1
vga.niosII.compent.v
- 在cyloneIIFPGA平台下设计完成测试通过的VGA控制器代码。显存留在系统的SDRAM中，用FIFO作为缓冲。-in cyloneIIFPGA platform design is completed tests through the VGA controller code. RAM in the system SDRAM, and use as a FIFO buffer.
display
- 在spartan3e开发板的数码管部分显示数字-Spartan3e development board in the digital control section shows the number
Traffic_llight_controller
- Consider the following variation on the traffic light controller problem. A North-South road intersects an East-West road. In addition to the Red/Yellow/Green traffic lights, the N-S road has green left-turn arrows. The arrows work as follows. Wit
chap5
- 本程序是关于学习VERILOG语言的案例，方便读者快速掌握VERILOG语言的基本语法，操作等-This program is about learning the language of the case VERILOG to allow readers to quickly master the basic syntax of the language VERILOG, operation, etc.
BAK
- 实现可判断闰年的万年历，未使用除法运算，可用于多种综合工具-This module work as a calendar which can judge leapyears without divider
musicplayer
- 乐曲演奏 分频 vhdl xilinx-Music performance divide
Amateurcodekommentar.c
- Hello, i am 12 this is my first program
DAC0832
- DAC0832的VHDL程序与仿真。 目的是产生频率为762.9Hz的锯齿波。-DAC0832 and simulation of VHDL programs. The purpose is to generate the sawtooth frequency of 762.9Hz.